UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 616

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.16.1 Master operation in single master system
616
Note Release the I
Remarks 1. For the transmission and reception formats, conform to the specifications of the product in
product in communication.
For example, when the EEPROM
port and output clock pulses from that output port until when the SDA0n pin is constantly high level.
2. n = 0 to 2, m = 0, 1
communication.
2
C0n bus (SCL0n, SDA0n pins = high level) in conformity with the specifications of the
No
No
Figure 17-18. Master Operation in Single Master System
ACKEn = WTIMn = SPIEn = 1
Set STCENn, IICRSVn = 0
Transfer completed?
interrupt occurred?
Initialize I
interrupt occurred?
interrupt occurred?
OCKSm ← XXH
IICCLn ← XXH
IICXn ← 0XH
SVAn ← XXH
IICCn ← XXH
STCENn = 1?
IICFn ← 0XH
ACKDn = 1?
ACKDn = 1?
Restarted?
TRCn = 1?
Write IICn
Write IICn
IICEn = 1
Set ports
SPTn = 1
STTn = 1
INTIICn
INTIICn
INTIICn
START
2
C bus
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Preliminary User’s Manual U18953EJ1V0UD
Note
TM
outputs a low level to the SDA0n pin, set the SCL0n pin to the output
Waiting for stop condition detection
Yes
No
No
No
No
No
No
Communication start preparation
(stop condition generation)
Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
Waiting for ACK detection
Transmission start
Waiting for data transmission
CHAPTER 17 I
SPTn = 1
2
END
C mode before this function is used.
2
C BUS
WTIMn = WRELn = 1
Transfer completed?
interrupt occurred?
interrupt occurred?
WRELn = 1
ACKEn = 1
ACKEn = 0
WTIMn = 0
Read IICn
INTIICn
INTIICn
Yes
Yes
Yes
No
No
No
Reception start
Waiting for
data reception
Waiting for ACK detection

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