UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 720

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode
input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal
interrupt request signal from the peripheral functions operable in the sub-IDLE mode/low-voltage sub-IDLE mode, or
reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). The
PLL returns to the operating status it was in before the sub-IDLE mode was set. It returns to the stop status in the
low-voltage sub-IDLE mode.
operation mode is set.
mode.
720
Non-maskable interrupt request
signal
Maskable interrupt request signal
The sub-IDLE mode/low-voltage sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set.
When the low-voltage sub-IDLE mode is released by an interrupt request signal, the low-voltage subclock
For releasing low-voltage subclock operation mode, see 21.7.3 Releasing low-voltage subclock operation
(1) Releasing sub-IDLE mode/low-voltage sub-IDLE by non-maskable interrupt request signal or
(2) Releasing sub-IDLE mode/low-voltage sub-IDLE by reset
unmasked maskable interrupt request signal
The sub-IDLE mode/low-voltage sub-IDLE is released by a non-maskable interrupt request signal or an
unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal.
If the sub-IDLE mode/low-voltage sub-IDLE is set in an interrupt servicing routine, however, an interrupt
request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
The same operation as the normal reset operation is performed.
Release Source
is issued, the sub-IDLE mode/low-voltage sub-IDLE is released, but that interrupt request signal is not
acknowledged. The interrupt request signal itself is retained.
is issued (including a non-maskable interrupt request signal), the sub-IDLE mode/low-voltage sub-IDLE
mode is released and that interrupt request signal is acknowledged.
Table 21-11. Operation After Releasing Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode
2. When the sub-IDLE mode/low-voltage sub-IDLE mode is released, 12 cycles of the
PSC.INTM bits to 1 becomes invalid and sub-IDLE mode/low-voltage sub-IDLE mode is
not released.
subclock (about 366
sub-IDLE mode/low-voltage sub-IDLE is generated to when the mode is released.
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Interrupt Enabled (EI) Status
by Interrupt Request Signal
µ
s) elapse from when the interrupt request signal that releases the
The next instruction is executed.
Interrupt Disabled (DI) Status