UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 607

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.12 Arbitration
the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is
adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2).
timing by which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which
releases the bus (n = 0 to 2).
clock, when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software (n = 0 to
2).
Transfer lines
When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before
When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the
Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth
For details of interrupt request timing, see 17.7 I
Master 1
Master 2
Remark
SDA0n
SDA0n
SDA0n
SCL0n
SCL0n
SCL0n
n = 0 to 2
Figure 17-14. Arbitration Timing Example
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 17 I
2
C Interrupt Request Signals (INTIICn).
2
C BUS
Master 1 loses arbitration
Hi-Z
Hi-Z
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