UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 767
UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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28.4.6 Pin connection
programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory
programming mode.
status as that immediately after reset.
acknowledge the status immediately after a reset.
When performing on-board writing, mount a connector on the target system to connect to the dedicated flash
In the flash memory programming mode, all the pins not used for flash memory programming become the same
(1) FLMD0 pin
(2) FLMD1 pin
Caution If the V
In the normal operation mode, input a voltage of V
programming mode, supply a write voltage of V
Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of V
must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see
28.5.5 (1) FLMD0 pin.
When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V
pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following
shows an example of the connection of the FLMD1 pin.
immediately after reset, isolate this signal.
DD
signal is input to the FLMD1 pin from another device during on-board writing and
V850ES/JG3-L
V850ES/JG3-L
FLMD0
Figure 28-11. FLMD0 Pin Connection Example
Figure 28-12. FLMD1 Pin Connection Example
FLMD1
Preliminary User’s Manual U18953EJ1V0UD
Therefore, pin handling is required when the external device does not
CHAPTER 28 FLASH MEMORY
Dedicated flash programmer connection pin
DD
Pull-down resistor (R
Pull-down resistor (R
level to the FLMD0 pin.
SS
level to the FLMD0 pin.
Other device
FLMD0
FLMD1
)
)
DD
is supplied to the FLMD0
In the flash memory
DD
level
767
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