UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 734

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

734
Clock monitor status
(1) Operation when main clock oscillation is stopped (CLME bit = 1)
(2) Clock monitor status after RESET input
Internal oscillation
Internal oscillation
RESF.CLMRF bit
(CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time)
CLM.CLME bit
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as
shown in Figure 23-2.
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1
by software at the end of the oscillation stabilization time of the main clock, monitoring is started.
CPU operation
Internal reset
Main clock
Main clock
RESET
signal
CLME
clock
clock
Figure 23-2. Reset Period Due to That Oscillation of Main Clock Is Stopped
Monitoring
operation
Normal
Figure 23-3. Clock Monitor Status After RESET Input
Reset
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 23 CLOCK MONITOR
stabilization time
Four internal oscillation clocks
Clock supply
Oscillation
stopped
Monitoring stopped
Normal operation
Set to 1 by software
Monitoring