UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 272

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

272
TPnCTL0
TPnCTL1
TPnIOC0
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
(c) TMPn I/O control register 0 (TPnIOC0)
Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1
TPnCE
0/1
0
0
TPnEST
Figure 7-31. Register Setting in Free-Running Timer Mode (1/2)
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnEEE
0/1
0
0
Preliminary User’s Manual U18953EJ1V0UD
0
0
0
TPnOL1
0/1
0
0
TPnCKS2 TPnCKS1 TPnCKS0
TPnOE1 TPnOL0
TPnMD2 TPnMD1 TPnMD0
0/1
0/1
1
0/1
0/1
0
TPnOE0
0/1
0/1
1
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
1, 0, 1:
Free-running mode
Select count clock
0: Stop counting
1: Enable counting
0: Operate with count
1: Count on external
clock selected by
TPnCKS0 to TPnCKS2 bits
event count input signal
Note