UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 673

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.6 In-service priority register (ISPR)
request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal
is set to 1 and remains set while the interrupt is serviced.
priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-
maskable interrupt servicing or exception processing.
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI)
Remark
status, the value of the ISPR register after the bits of the register have been set by
acknowledging the interrupt may be read. To accurately read the value of the ISPR register
before an interrupt is acknowledged, read the register while interrupts are disabled (DI).
n = 0 to 7 (priority level)
After reset:
ISPR
ISPRn
ISPR7
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
00H
<7>
0
1
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
R
ISPR6
<6>
Address:
Preliminary User’s Manual U18953EJ1V0UD
ISPR5
<5>
Priority of interrupt currently acknowledged
FFFFF1FAH
ISPR4
<4>
ISPR3
<3>
ISPR2
<2>
ISPR1
<1>
ISPR0
<0>
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