UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 14

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 630
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 653
14
17.7
17.8
17.9
17.10 Error Detection...................................................................................................................... 606
17.11 Extension Code..................................................................................................................... 606
17.12 Arbitration ............................................................................................................................. 607
17.13 Wakeup Function.................................................................................................................. 608
17.14 Communication Reservation............................................................................................... 609
17.15 Cautions ................................................................................................................................ 614
17.16 Communication Operations ................................................................................................ 615
17.17 Timing of Data Communication .......................................................................................... 623
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10 DMA Abort Factors............................................................................................................... 643
18.11 End of DMA Transfer............................................................................................................ 643
18.12 Operation Timing .................................................................................................................. 643
18.13 Cautions ................................................................................................................................ 648
19.1
19.2
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
I
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 604
Address Match Detection Method ...................................................................................... 606
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................609
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................613
17.16.1 Master operation in single master system................................................................................616
17.16.2 Master operation in multimaster system ..................................................................................617
17.16.3 Slave operation........................................................................................................................620
Features................................................................................................................................. 630
Configuration ........................................................................................................................ 631
Registers ............................................................................................................................... 632
Transfer Targets ................................................................................................................... 639
Transfer Modes ..................................................................................................................... 639
Transfer Types ...................................................................................................................... 640
DMA Channel Priorities........................................................................................................ 641
Time Related to DMA Transfer ............................................................................................ 641
DMA Transfer Start Factors................................................................................................. 642
Features................................................................................................................................. 653
Non-Maskable Interrupts ..................................................................................................... 657
19.2.1
19.2.2
19.2.3
2
C Interrupt Request Signals (INTIICn) .............................................................................. 584
Addresses................................................................................................................................577
Transfer direction specification ................................................................................................578
ACK .........................................................................................................................................579
Stop condition ..........................................................................................................................580
Wait state.................................................................................................................................581
Wait state cancellation method ................................................................................................583
Master device operation...........................................................................................................584
Slave device operation (when receiving slave address data (address match))........................587
Slave device operation (when receiving extension code) ........................................................591
Operation without communication............................................................................................595
Arbitration loss operation (operation as slave after arbitration loss).........................................595
Operation when arbitration loss occurs (no communication after arbitration loss) ...................597
Operation .................................................................................................................................659
Restore ....................................................................................................................................660
NP flag .....................................................................................................................................661
Preliminary User’s Manual U18953EJ1V0UD