UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 470

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

470
(1) UARTAn control register 0 (UAnCTL0)
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
(4) UARTAn option control register 0 (UAnOPT0)
(5) UARTAn status register (UAnSTR)
(6) UARTAn receive shift register
(7) UARTAn receive data register (UAnRX)
(8) UARTAn transmit shift register
(9) UARTAn transmit data register (UAnTX)
The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation.
The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn.
The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
The UAnOPT0 register is an 8-bit register used to control serial transfer for the UARTAn.
The UAnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one
of the reception error flags is set (to 1) upon occurrence of a reception error.
This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception
of 1 byte of data and detection of the stop bit, the receive data is transferred to the UAnRX register.
This register cannot be manipulated directly.
The UAnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in
the highest bit (when data is received LSB first).
In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the
UAnRX register in synchronization with the completion of shift-in processing of 1 frame.
Transfer to the UAnRX register also causes the reception complete interrupt request signal (INTUAnR) to be
output.
The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX
register into serial data.
When 1 byte of data is transferred from the UAnTX register, the shift register data is output from the TXDAn pin.
This register cannot be manipulated directly.
The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the
UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from
the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal
(INTUAnT) is generated.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Preliminary User’s Manual U18953EJ1V0UD