UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 780

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

29.1.4 Register
780
(1) On-chip debug mode register (OCDM)
Note RESET input sets this register to 01H. After reset by the WDT2RES signal, clock monitor (CLM), or low-
Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins
This register is used to specify whether a pin provided with an on-chip debug function is used as an on-chip
debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-down
resistor of the P05/INTP2/DRST pin.
This register is a special register and can be written only in a combination of specific sequences (see 3.4.7
Special registers).
The OCDM register can be written only while a low level is input to the DRST pin.
This register can be read or written in 8-bit or 1-bit units.
voltage detector (LVI), however, the value of the OCDM register is retained.
2. The DRST pin has an on-chip pull-down resistor. This resistor is disconnected when the
OCDM
after external reset, any of the following actions must be taken.
• Input a low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit. In this case, take the following actions.
OCDM0 flag is cleared to 0.
After reset: 01H
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin to low level until <1> is completed.
OCDM0
0
1
0
DRST
Note
Selects normal operation mode (in which a pin that functions alternately
as on-chip debug function pin is used as a port/peripheral function pin) and
disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin.
When DRST pin is low:
Normal operation mode (in which a pin that functions alternately as an
on-chip debug function pin is used as a port/peripheral function pin)
When DRST pin is high:
On-chip debug mode (in which a pin that functions alternately as an
on-chip debug function pin is used as an on-chip debug mode pin)
CHAPTER 29 ON-CHIP DEBUG FUNCTION
R/W
0
Preliminary User’s Manual U18953EJ1V0UD
Address: FFFFF9FCH
0
10 to 100 kΩ
(30 kΩ (TYP.))
OCDM0 flag
(1: Pull-down ON, 0: Pull-down OFF)
0
Operation mode
0
0
0
OCDM0
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