UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 416

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation
the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After
this, the operation of watchdog timer 2 cannot be stopped.
interval.
After the count operation has started, write ACH to WDTE within the loop detection time interval.
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and
WDTM2.WDM20 bits.
after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation
clock.
From INTWDT2 signal.
416
(2) Watchdog timer enable register (WDTE)
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again.
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 19.2.2 (2)
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
3. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
4. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
WDTE
forcibly output.
overflow signal is forcibly output.
register only once, or write data to the WDTM2 register only twice.
However, when watchdog timer 2 is set to stop operation, an overflow signal is not
generated even if data is written to the WDTM2 register only twice, or a value other than
“ACH” is written to the WDTE register only once.
After reset: 9AH
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
R/W
Preliminary User’s Manual U18953EJ1V0UD
Address: FFFFF6D1H