UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 495

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) Baud rate
The baud rate is obtained by the following equation.
The baud rate error is obtained by the following equation.
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate using the above equation).
Remark
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate the baud rate error using the above equation).
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
Baud rate =
Baud rate =
Error (%) =
Error (%) =
2. The baud rate error during reception must satisfy the range indicated in (5) Allowable
f
f
m = Value set using the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits (m = 0 to 10)
k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4 to 255)
UCLK
XX
: Main clock frequency
receiving side.
baud rate range during reception.
= Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
=
Actual baud rate (baud rate with error)
2
2 × k × Target baud rate
f
2 × k
2
UCLK
Target baud rate (correct baud rate)
m+1
m+1
f
XX
× k
× k × Target baud rate
[bps]
[bps]
Preliminary User’s Manual U18953EJ1V0UD
f
UCLK
f
XX
− 1 × 100 [%]
− 1 × 100 [%]
− 1 × 100 [%]
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