UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 657

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.2 Non-Maskable Interrupts
disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request
signals.
edge detection”.
the WDTM2.WDM21 and WDTM2.WDM20 bits are set to “01”.
is serviced, as follows (the interrupt request signal with the lower priority is ignored).
A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt
This product has the following two non-maskable interrupt request signals.
• NMI pin input (NMI)
• Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2)
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no
The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when
If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority
INTWDT2 > NMI
If a new NMI or INTWDT2 request signal is issued while an NMI is being serviced, it is serviced as follows.
(1) If new NMI request signal is issued while NMI is being serviced
(2) If INTWDT2 request signal is issued while NMI is being serviced
The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI
request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI
instruction has been executed).
The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The
pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced
(after the RETI instruction has been executed).
If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is
executed (the NMI servicing is stopped).
Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request
Figure 19-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2)
signal (INTWDT2), see 19.2.2 (2) From INTWDT2 signal.
(a) NMI and INTWDT2 request signals generated at the same time
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
NMI and
(generated simultaneously)
INTWDT2 requests
Preliminary User’s Manual U18953EJ1V0UD
Main routine
System reset
INTWDT2 servicing
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