UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 171

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.5
5.5.1
5.5.2
size can be set to 8 bits and 16 bits only.
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
The following table shows the number of basic clocks required for accessing each resource.
Notes 1. Increases by 1 if a conflict with a data access occurs.
Remark
Each external memory area selected by memory block n can be set by using the BSC register. However, the bus
The external memory area of the V850ES/JG3-L is selected by memory blocks 0 to 3.
(1) Bus size configuration register (BSC)
Bus Access
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
Caution Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
Number of clocks for access
Bus size setting function
2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected.
Unit: Clocks/access
After reset:
BSC
access an external memory area until the initial settings of the BSC register are complete.
Area (Bus Width)
BSn0
15
5555H
0
7
0
0
1
Memory block 3
8 bits
16 bits
BS30
14
1
6
R/W
Data bus width of
CHAPTER 5 BUS CONTROL FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Internal ROM (32 Bits)
Address:
13
0
5
0
Memory block 2
1
2
3
memory block n
BS20
FFFFF066H
12
1
4
11
0
0
3
space (n = 0 to 3)
Memory block 1
Internal RAM (32 Bits)
BS10
10
1
2
1
2
Note 1
Note 1
1
0
1
0
9
Memory block 0
BS00
External Memory (16 Bits)
1
0
8
3 + n
3 + n
3 + n
Note 2
Note 2
Note 2
171

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