UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 576

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6 I
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”
generated on the I
bit data).
pin’s low-level period can be extended and a wait state can be inserted (n = 0 to 2).
17.6.1 Start condition
The start condition for the SCL0n and SDA0n pins is a signal that the master device outputs to the slave device when
starting a serial transfer. The slave device can defect the start condition (n = 0 to 2).
bit = 1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0 to 2).
576
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-
The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n
A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level.
A start condition is output when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn
Caution When the IICCn.IICEn bit of the V850ES/JG3-L is set to 1 while communications with other
2
C Bus Definitions and Control Methods
devices are in progress, the start condition may be detected depending on the status of the
communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are
high level.
SDA0n
SCL0n
2
C bus’s serial data bus is shown below.
Start
condition
Address
1 to 7
Figure 17-7. I
SDA0n
SCL0n
2
C bus’s serial data communication format and the signals used by the I
R/W
Preliminary User’s Manual U18953EJ1V0UD
8
Figure 17-8. Start Condition
H
ACK
CHAPTER 17 I
2
C Bus Serial Data Transfer Timing
9
1 to 8
Data
2
C BUS
ACK
9
1 to 8
Data
ACK
9
Stop
condition
2
C bus.