UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 519

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIBn pin capture
INTCBnR signal
(2) Operation timing
CBnTSF bit
SCKBn pin
SOBn pin
SIBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CBnCTL0 register, and select the transmission/reception mode and MSB first at the
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and start
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
(6) When transmission/reception of the transfer data length set with the CBnCTL2 register is completed,
(7) Read the CBnRX register.
(8) To continue transmission/reception, write the transmit data to the CBnTX register again.
(9) Read the CBnRX register.
(10) To end transmission/reception, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0,
Remark
timing
f
same time as enabling the operation of the communication clock (f
transmission/reception.
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
stop the serial clock output, transmit data output, and data capturing, generate the reception
completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the
CBnTSF bit to 0.
and the CBnCTL0.CBnRXE bit = 0.
XX
/2, and master mode.
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7
Bit 7
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Preliminary User’s Manual U18953EJ1V0UD
Bit 1
Bit 1
(6)
(7)
Bit 0
Bit 0
(8)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
CCLK
Bit 4
Bit 4
).
Bit 3 Bit 2
Bit 3 Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
(9)
(10)
CCLK
) =
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