UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 620

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.16.3 Slave operation
(processing requiring a significant change of the operation status, such as stop condition detection during
communication) is necessary.
that the INTIICn interrupt servicing performs only status change processing and that the actual data communication is
performed during the main processing.
transmitting these flags to the main processing instead of INTIICn signal.
(1) Communication mode flag
(2) Ready flag
(3) Communication direction flag
using the communication mode flag and ready flag (the processing of the stop condition and start condition is
performed by interrupts, conditions are confirmed by flags).
device stops returning ACK, transfer is complete.
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The following shows the processing procedure of the slave operation.
Basically, the operation of the slave device is event-driven.
The following description assumes that data communication does not support extension codes. Also, it is assumed
Therefore, the following three flags are prepared so that the data transfer processing can be performed by
The following shows the operation of the main processing block during slave operation.
Start I
For transmission, repeat the transmission operation until the master device stops returning ACK. When the master
This flag indicates the following communication statuses.
Clear mode:
Communication mode: Data communication in progress (valid address detection stop condition detection, ACK
This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during
normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block.
The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is
transmitted without clear processing (the address match is regarded as a request for the next data).
This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit.
2
C0n and wait for the communication enabled status. When communication is enabled, perform transfer
I
2
C
Data communication not in progress
from master not detected, address mismatch)
Figure 17-20. Software Outline During Slave Operation
INTIICn signal
Setting, etc.
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 17 I
Interrupt servicing
Setting, etc.
Data
2
C BUS
Therefore, processing by an INTIICn interrupt
Flag
Main processing