UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 168

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
5.2.1
5.2.2
168
AD0 to AD15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDRQ
HLDAK
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
HLDRQ
HLDAK
The pins used to connect an external device are listed in the table below.
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Caution When a write access is performed to the internal ROM area, address, data, and control signals
For the pin status of the V850ES/JG3-L in each operation mode, see 2.2 Pin States.
Address/data bus
(AD15 to AD0)
Address bus (A21 to A16)
Address bus (A15 to A0)
Control signal
Bus Control Pins
Bus Control Pin
Bus Control Pin
Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
Pin status in each operation mode
Bus Control Pin
are activated in the same way as access to the external memory area.
PDL0 to PDL15
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
PDL0 to PDL15
P90 to P915
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCM3
PCM2
Alternate-Function Pin
Alternate-Function Pin
Low level
Low level
High level
Inactive
Internal ROM/RAM
Table 5-2. External Control Pins (Separate Bus)
Table 5-1. Bus Control Pins (Multiplexed Bus)
CHAPTER 5 BUS CONTROL FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Separate Bus Mode
Undefined
High level
Undefined
Inactive
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Peripheral I/O
Address/data bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
Data bus
Address bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Bus hold control
Hi-Z
Low level
Low level
Inactive
Internal ROM/RAM
Multiplexed Bus Mode
Function
Function
Hi-Z
Undefined
Undefined
Inactive
Peripheral I/O