HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 678

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
20.5.3
Figure 20.5 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then changing the RES pin from low to high.
20.5.4
Timing of Transition to Hardware Standby Mode:
1. To retain RAM contents with the RAME bit set to 1 in SYSCR
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
Rev.7.00 Dec. 24, 2008 Page 622 of 698
REJ09B0074-0700
Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in
figure 20.6. After STBY has gone low, RES has to wait for at least 0 ns before becoming high.
not need to be retained
RES does not have to be driven low as in the above case.
Oscillator
RES
STBY
Hardware Standby Mode Timing
Hardware Standby Mode Timings
STBY
RES
Figure 20.6 Timing of Transition to Hardware Standby Mode
Figure 20.5 Hardware Standby Mode Timing (Example)
t
1
≥ 10 t
cyc
t
2
≥ 0 ns
Oscillation
stabilization
time t
OSC1
Reset exception
handling

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