HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 434

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.7.00 Dec. 24, 2008 Page 378 of 698
REJ09B0074-0700
Bit
5
4
Bit Name Initial Value R/W
ORER
FER
0
0
R/(W)*
R/(W)*
1
1
Description
Overrun Error
[Setting condition]
•
[Clearing condition]
•
Framing Error
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is retained
in RDR, and the data received subsequently is lost.
Also, subsequent serial reception cannot be
continued while the ORER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
When 0 is written to ORER after reading ORER = 1*
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
for a value of 0; the second stop bits not checked. If
a framing error occurs, the receive data is transferred
to RDR but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued
while the FER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
When 0 is written to FER after reading FER = 1*
The FER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
2
2