HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 459

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
12.4
Figure 12.5 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmission line is
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial
communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-
duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be
read from or written during transmission or reception, enabling continuous data transfer.
Serial
data
Operation in Asynchronous Mode
1
Start
bit
1 bit
0
Figure 12.5 Data Format in Asynchronous Communication
LSB
D0
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
One unit of transfer data (character or frame)
D2
Transmit/receive data
D3
7 or 8 bits
D4
D5
D6
Rev.7.00 Dec. 24, 2008 Page 403 of 698
MSB
D7
Parity
bit
1 bit,
or none
0/1
1
Stop bit
1 or
2 bits
1
REJ09B0074-0700
Idle state
(mark state)
1

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