HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 257

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DREQ Signal Level Activation Timing (Normal Mode): Set the DTA bit for the channel for
which the DREQ signal is selected to 1.
Figure 7.19 shows an example of DREQ level activated normal mode transfer.
DREQ signal sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ signal low level is sampled while acceptance by means of the DREQ signal is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. Acceptance resumes after the end of the write cycle, DREQ signal low level
sampling is performed again, and this operation is repeated until the transfer ends.
Note: The DREQ signal of this chip is an internal signal of chip, so it is not output from the pin.
Address bus
DMA control
Channel
[1]
[2] [5]
[3] [6]
[4] [7]
DREQ
Figure 7.19 Example of DREQ Level Activated Normal Mode Transfer
φ
Acceptance after transfer enabling; the DREQ signal low level is sampled on the rising
edge of f, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle.
Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ signal low level is sampled on the rising edge of φ, and the request
is held.)
Idle
Bus release
Minimum of 2 cycles
[1]
Request
[2]
Read
[3]
Request clear period
Transfer
source
DMA
read
Write
Acceptance resumes
DMA
write
Transfer
destination
Idle
Minimum of 2 cycles
[4]
Request
Bus
release
Rev.7.00 Dec. 24, 2008 Page 201 of 698
[5]
Read
[6]
Request clear period
Transfer
source
DMA
read
Write
Acceptance resumes
Transfer
destination
DMA
write
Idle
REJ09B0074-0700
[7]
Bus
release