HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 576

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Universal Serial Bus (USB)
14.6
DMA Transfer Specifications
Two methods of USB request and auto request are available for the DMA transfer of USB data.
14.6.1
DMAC Transfer by USB Request
(1) Overview
Only normal mode in full address mode (cycle steal mode) supports the transfer by a USB request
of the on-chip DMAC. Endpoints that can be transferred by the on-chip DMAC are EP1 and EP2
in Bulk transfer (corresponding registers are UEDR1 and UEDR2). In DMA transfer, the USB
module must be accessed as an external device in area 6. The USB module cannot be accessed as a
device with external ACK (single-address transfer cannot be performed). 0-byte data transfer to
EP2 is ignored even if the DMA transfer is enabled by setting the EP2T1 bit in UDMAR to 1.
(2) On-Chip DMAC Settings
The on-chip DMAC must be specified as follows: A USB request (DREQ signal is used), activated
by low-level input, byte size, full-address mode transfer, and the DTA bit in DMABCR = 1. After
completing the DMA transfer of specified times, the DMAC automatically stops. Note, however,
that the USB module keeps the DREQ signal low while data to be transferred by the on-chip
DMAC remains regardless of the DMAC status.
(3) EP1 DMA Transfer
The EP1T1 bit in UDMAR enables the DMA transfer. The EP1T0 bit in UDMAR specifies the
DREQ signal to be used by the DMA transfer. When 1 is written to the EP1T1 bit, the DREQ
signal is driven low if at least one of EP1 data FIFOs is empty; the DREQ signal is driven high if
both EP1 data FIFOs are full.
(a) EP1PKTE in UTRG0
When DMA transfer is performed on EP1 transmit data, the USB module automatically performs
the same processing as writing 1 to EP1PKTE if one data FIFO (64 bytes) becomes full.
Accordingly, to transfer data of integral multiples of 64 bytes, the user needs not to write 1 to
EP1PKTE. To transfer data of less than 64 bytes, the user must write 1 to EP1PKTE using the
DMA transfer end interrupt of the on-chip DMAC. If the user writes 1 to EP1PKTE in cases other
than the case when data of less than 64 bytes is transferred, excess transfer occurs and correct
operation cannot be guaranteed.
Figure 14.22 shows an example for transmitting 150 bytes of data from EP1 to the host. In this
case, internal processing as the same as writing 1 to EP1PKTE is automatically performed twice.
This kind of internal processing is performed when the currently selected data FIFO becomes full.
Rev.7.00 Dec. 24, 2008 Page 520 of 698
REJ09B0074-0700