HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 231

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit Bit Name Initial Value R/W
6
5
4
DTE1
DTME0
DTE0
0
0
0
R/W
R/W
R/W
Data Transfer Enable
When DTE = 0, data transfer is disabled and the activation
source selected by the data transfer factor setting is ignored.
If the activation source is an internal interrupt, an interrupt
request is issued to the CPU. If the DTIE bit is set to 1 when
DTE = 0, the DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt request to the
CPU.
The conditions for the DTE bit being cleared to 0 are as
follows:
•
•
•
When DTE = 1 and DTME = 1, data transfer is enabled and
the DMAC waits for a request by the activation source
selected by the data transfer factor setting. When a request is
issued by the activation source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
•
Data Transfer Enable 1
Enables or disables data transfer on channel 1.
0: Data transfer disabled
1: Data transfer enabled
Data Transfer Master Enable 0
Enables or disables data transfer on channel 0.
0: Data transfer disabled. In burst mode, cleared to 0 by an
1: Data transfer enabled
Data Transfer Enable 0
Enables or disables data transfer on channel 0.
0: Data transfer disabled
1: Data transfer enabled
Description
NMI interrupt
When initialization is performed
When the specified number of transfers have been
completed
When 0 is written to the DTE bit to forcibly abort the
transfer, or for a similar reason
When 1 is written to the DTE bit after the DTE bit is read
as 0
Rev.7.00 Dec. 24, 2008 Page 175 of 698
REJ09B0074-0700