HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 249

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission
complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture
A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.13 shows
an example of the setting procedure for block transfer mode.
Figure 7.13 Example of Block Transfer Mode Setting Procedure
Set number of transfers
and transfer destination
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address in MARA, and
[3] Set the transfer source address in ETCRAH
[4] Set each bit in DMACRA and DMACRB.
[5] Read the DTE = 0 and DTME = 0 in
[6] Set each bit in DMABCRL.
the transfer destination address in MARB.
and ETCRAL. Set the number of transfers in
ETCRB.
DMABCRL.
· Set the FAE bit to 1 to select full address
· Specify enabling or disabling of internal
· Set the transfer data size with the DTSZ bit.
· Specify whether MARA is to be incremented,
· Set the BLKE bit to 1 to select block transfer
· Specify whether the transfer source or the
· Specify whether MARB is to be incremented,
· Select the activation source with bits DTF3
· Specify enabling or desabling of transfer end
· Set both the DTME bit and the DTE bit to 1
mode.
interrupt clearing with the DTA bit.
decremented, or fixed, with the SAID and
SAIDE bits.
mode.
transfer destination is a block area with the
BLKDIR bit.
decremented, or fixed, with the DAID and
DAIDE bits.
to DTF0.
interrupts to the CPU with the DTIE bit.
to enable transfer.
Rev.7.00 Dec. 24, 2008 Page 193 of 698
REJ09B0074-0700