HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 466

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.6
Figure 12.11 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Table 12.11 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.12 shows a sample flow chart
for serial data reception.
Rev.7.00 Dec. 24, 2008 Page 410 of 698
REJ09B0074-0700
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
RDRF
FER
Serial Data Reception (Asynchronous Mode)
1
Start
bit
0
D0
Figure 12.11 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
RXI interrupt
request
generated
Parity
bit
0/1
Stop
bit
1
Start
bit
0
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
D0
D1
Data
D7
Parity
bit
0/1
ERI interrupt request
generated by framing
error
Stop
bit
0
Idle state
(mark state)
1