HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 539

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.18 USB Interrupt Flag Register 3 (UIFR3)
UIFR3 is an interrupt flag register indicating the USB status. If the corresponding bit is set to 1,
the corresponding EXIRQ0, EXIRQ1, or IRQ6 interrupt is requested to the CPU. VBUSi, SPRSi,
SETC, SOF, and CK48READY flags can be cleared by writing 0 to them. Writing 1 to them is
invalid and causes no operation. Consequently, to clear a flag, write 0 to the corresponding bit and
1 to all the other bits. (For example, write H'DF to clear bit 5.) The bit-clear instruction is a
read/modify/write instruction, so if a new flag is set between the read and write operations, there is
a danger that it may be cleared erroneously. Therefore, do not use the bit-clear instruction to clear
bits in this interrupt flag resister. VBUSs and SPRSs are status bits and cannot be cleared.
Bit Bit Name
7
6
5
4
3
CK48READY 0
SOF
SETC
—
SPRSs
Initial Value R/W
0
0
0
0
R/(W)* USB Operating Clock (48 MHz) Stabilization Detection
R/(W)* Start of Frame Packet Detection
R/(W)* Set_Configuration Command Detection
R
R
Description
Set to 1 when the USB operating clock (48 MHz)
stabilization time has been automatically counted after
USB module stop mode cancellation. The
corresponding interrupt output is EXIRQ0 or EXIRQ1.
CK48READY can also operate in the USB interface
software reset state (the UIFRST bit in UCTLR is set
to 1).
Refer to the UCKS3 to UCKS0 bits in section 14.3.1,
USB Control Register (UCTLR).
Set to 1 if the Start of Frame (SOF) packet is
detected. The corresponding interrupt output is
EXIRQ0 or EXIRQ1.
Set to 1 if the Set_Configuration command is
detected. The corresponding interrupt output is
EXIRQ0 or EXIRQ1.
Reserved
This bit is always read as 0 and cannot be modified.
Suspend/Resume Status
SPRSs indicates the suspend/resume status.
However, an interrupt cannot be requested by SPRSs.
0: Indicates that the bus is in the normal state.
1: Indicates that the bus is in the suspend state.
Rev.7.00 Dec. 24, 2008 Page 483 of 698
REJ09B0074-0700