HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 636

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.7.00 Dec. 24, 2008 Page 580 of 698
REJ09B0074-0700
Note: 7. Write Pulse Width
Number of Writes n
N1+N2-2
N1+N2-1
N1+N2
N1+1
N1+2
N1+3
N1-1
N1
1
2
Write pulse application subroutine
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
Clear PSU1 bit in FLMCR1
Reprogram data storage
Additional-programming
Set PSU1 bit in FLMCR1
Wait (z0), (z1), or (z2) µs
Reprogram Data Computation Table
Clear P1 bit in FLMCR1
Program data storage
Subroutine Write Pulse
Set P1 bit in FLMCR1
data storage area
Original Data
area (128 bytes)
area (128 bytes)
(128 bytes)
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of z0 or z1 is applied according to the progress of the programming operation. See note 7 for details of the pulse widths. When writing of additional-
6. x, y, z0, z1, z2, α, β, γ, ε, η, θ, N1, and N2 are shown in section 22.7, Flash Memory Characteristics.
WDT enable
Disable WDT
Program
Wait (y) µs
Wait (α) µs
Wait (β) µs
(D)
RAM
End Sub
0
0
1
1
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
programming data is executed, a z2 write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
P1 bit set time (µs)
z0
z0
z0
z0
z1
z1
z1
z1
z1
z1
Verify Data
Figure 17.13 Program/Program-Verify Flowchart
Re -program
(V)
0
1
0
1
z2
z2
z2
z2
_
_
_
_
_
_
*
6
Reprogram Data
*
*
*
*
6
5
6
6
*
(X)
6
1
0
1
1
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Increment address
Comments
Successively write 128-byte data from additional-
Apply Write Pulse (Additional programming) z2μs
programming data area in RAM to flash memory
No
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Apply
Additional-Programming Data Computation Table
Clear SWE1 bit in FLMCR1
Reprogram Data
Set SWE1 bit in FLMCR1
Clear PV1 bit in FLMCR1
Reprogram data computation
data verification completed?
Set PV1 bit in FLMCR1
Start of programming
Write pulse Z0
End of programming
(X')
Read verify data
0
0
1
1
Yes
Yes
Wait (x) µs
Wait (γ) µs
Wait (ε) µs
Write data =
Wait (η) µs
Wait (θ) µs
verify data?
Yes
128-byte
START
N1 ≥
N1
m = 0 ?
m = 0
n = 1
≥
n ?
n?
Yes
Yes
Sub-Routine-Call
Sub-Routine-Call
Verify Data
µs
or Z1
(V)
0
1
0
1
µs
No
No
No
Programming Data (Y)
*
*
No
*
*
*
*
*
*
See Note 7 for pulse width
6
Additional-
2
3
6
6
6
6
6
*
*
*
4
0
1
1
1
1
4
*
*
*
m = 1
4
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
6
Clear SWE1 bit in FLMCR1
Programming failure
n ≥ (N1 + N2)?
Wait (θ) µs
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Yes
Comments
No
n ← n + 1
*
Reprogram
6