HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 166

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Selection of Interrupt Source: An activation factor is directly input to each channel of the
DMAC. The activation factors for each channel of the DMAC are selected by the DTF3 to DTF0
bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation
factors are managed by the DMAC. By setting the DTA bit to 1, the interrupt factor which was the
activation factor for that DMAC cannot act as the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC is CPU interrupt request.
Determination of Priority: The activation source is directly input to each channel of DMAC.
Operation Order: If the same interrupt is selected as the DMAC activation factor or CPU
interrupt factor, these operate independently. They operate in accordance with the respective
operating states and bus priorities.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC's DMABCR.
Rev.7.00 Dec. 24, 2008 Page 110 of 698
REJ09B0074-0700
peripheral
On-chip
module
IRQ
interrupt
Interrupt source
clear signal
Interrupt
request
Figure 5.7 Interrupt Control for DMAC
Interrupt controller
Selection
circuit
Disenable
signal
DMAC
Determination of
Control logic
priority
Clear
signal
CPU interrupt
request vector
number
I, I2 to I0
CPU