HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 156

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
The set timing for IRQnF is shown in figure 5.3.
The detection of IRQn interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt
request flag is set when the setting condition is satisfied, regardless of IER settings. Accordingly,
refer to only necessary flags.
5.4.2
The sources for internal interrupts from on—chip peripheral modules have the following features:
• For each on—chip peripheral module there are flags that indicate the interrupt request status,
• The interrupt priority level can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC is activated by an interrupt request, it is not affected by the interrupt control
Rev.7.00 Dec. 24, 2008 Page 100 of 698
REJ09B0074-0700
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
mode or CPU interrupt mask bit.
IRQn
input pin
IRQnF
Internal Interrupts
Note: n = 7 to 0
Figure 5.3 Timing of Setting IRQnF

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