HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 264

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2. If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
7.6.2
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
•
7.6.3
When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-
detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip
peripheral modules operate on a high-speed clock.
Consequently, if the period in which the relevant interrupt source is cleared by the CPU or another
DMAC channel, and the next interrupt is generated, is less than one state with respect to the
DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be
ignored.
Rev.7.00 Dec. 24, 2008 Page 208 of 698
REJ09B0074-0700
register is read as shown in figure 7.26.
Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
For details, refer to section 20, Power-Down Modes.
Note:
DMA internal
address
Module Stop
Medium-Speed Mode
DMA control
DMA register
operation
Figure 7.26 Contention between DMAC Register Update and CPU Read
φ
The lower word of MAR is the updated value after the operation in [1].
MAR upper
word read
Idle
CPU longword read
MAR lower
word read
[1]
Transfer
source
Read
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle