HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 280

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
8.2.2
P3DR stores output data for the port 3 pins.
8.2.3
PORT3 indicates the pin states of the port 3.
Note: * Determined by the states of pins P36 and P32 to P30.
Rev.7.00 Dec. 24, 2008 Page 224 of 698
REJ09B0074-0700
Bit
7
6
5 to
3
2
1
0
Bit
7
6
5 to
3
2
1
0
Bit Name Initial Value
P36DR
P32DR
P31DR
P30DR
Bit Name Initial Value
P36
P32
P31
P30
Port 3 Data Register (P3DR)
Port 3 Register (PORT3)
Undefined
0
Undefined
0
0
0
Undefined
⎯*
Undefined
⎯*
⎯*
⎯*
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
Description
Reserved
This bit is undefined and cannot be modified.
Stores output data for a pin that functions as a general
output port.
Reserved
These bits are undefined and cannot be modified.
Store output data for a pin that functions as a general
output port.
Description
Reserved
This bit is undefined.
If the port 3 is read while P3DDR bits are set to 1, the
P3DR value is read. If the port 3 is read while P3DDR bits
are cleared to 0, the pin states are read.
Reserved
These bits are undefined.
If the port 3 is read while P3DDR bits are set to 1, the
P3DR value is read. If the port 3 is read while P3DDR bits
are cleared to 0, the pin states are read.

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