HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 390

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
data prior to the write. Figure 9.48 shows the timing in this case.
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T
Figure 9.49 shows the timing in this case.
Rev.7.00 Dec. 24, 2008 Page 334 of 698
REJ09B0074-0700
2
1
state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.48 Contention between Buffer Register Write and Compare Match
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 9.49 Contention between TGR Read and Input Capture
N
X
TGR write cycle
TGR read cycle
Buffer register
T
T
TGR address
1
1
address
M
T
T
2
2
M
M
N
Buffer register write data

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