HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 531

IC H8S MCU FLASH 128K 100-TQFP

HD64F2218UTF24

Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of HD64F2218UTF24

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24
Manufacturer:
RENESAS
Quantity:
14
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
14.3.5
UFCLR0 is a one-shot register used to clear the FIFO for each endpoint EP0 to EP3. Writing 1 to a
bit clears the data in the corresponding FIFO.
For IN FIFO, writing 1 to a bit in UFCLR0 clears the data for which the corresponding PKTE bit
in UTRG0 is not set to 1 after data write, or data that is validated by setting the corresponding
PKTE bit in UTRG0.
For OUT FIFO, writing 1 to a bit in UFCLR0 clears data that has not been fixed during reception
or received data for which the corresponding RDFN bit is not set to 1. Accordingly, care must be
taken not to clear data that is currently being received or transmitted. EP1 and EP2, having a dual-
FIFO configuration, are cleared by entire FIFOs. Note that this trigger does not clear the
corresponding interrupt flag. For details, see section 2.9.4, Accessing Registers Containing Write-
Only Bits.
Bit
7, 6
5
4
3
2
1
Bit Name
EP2CLR
EP1CLR
EP3CLR
EP0oCLR
EP0iCLR
USB FIFO Clear Register 0 (UFCLR0)
Initial Value R/W
All 0
0
0
0
0
0
R
W
W
W
W
W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
EP2 Clear*
0: Performs no operation.
1: Clears EP2 OUT FIFO.
EP1 Clear
0: Performs no operation.
1: Clears EP1 IN FIFO.
EP3 Clear
0: Performs no operation.
1: Clears EP3 IN FIFO.
EP0o Clear
0: Performs no operation.
1: Clears EP0o OUT FIFO.
EP0i Clear
0: Performs no operation.
1: Clears EP0i IN FIFO.
Rev.7.00 Dec. 24, 2008 Page 475 of 698
REJ09B0074-0700

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