HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 253

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.4.9
Short Address Mode: Figure 7.15 shows a transfer example in which TEND* output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND* output is enabled, TEND* output goes low in the transfer cycle in
which the transfer counter reaches 0.
Note: * This LSI does not support TEND output.
Address bus
Note: * This LSI does not support TEND output.
TEND*
HWR
LWR
DMAC Bus Cycles (Dual Address Mode)
RD
φ
Bus release
Figure 7.15 Example of Short Address Mode Transfer
DMA read
DMA write
Bus release
DMA read DMA write
Rev.7.00 Dec. 24, 2008 Page 197 of 698
Bus release
DMA read DMA write
Last transfer cycle
REJ09B0074-0700
DMA
dead
Bus release