IPR-NIOS Altera, IPR-NIOS Datasheet - Page 96

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–50
Nios II Processor Reference Handbook
1
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Table 3–36. Example of Illegal RIL Assignment
Table 3–37. Example of Legal RIL Assignment
Noninterrupt exception handlers must always save and restore the register contents,
because they run in the normal register set.
Multiple interrupts can share a register set, with some loss of performance. There are
two techniques for sharing register sets:
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Multiple interrupts with different RILs can be assigned to a single shadow register
set. However, with multiple register sets, you must not allow the RILs assigned to
one shadow register set to overlap the RILs assigned to another register set.
Table 3–36
preemption within a register set is enabled.
Set status.RSIE to 0. When an ISR is running in a given register set, the processor
does not take any maskable interrupt assigned to the same register set. Such
interrupts must wait for the running ISR to complete, regardless of their interrupt
level.
1
Ensure that each ISR saves and restores registers on entry and exit, and set
status.RSIE to 1 after registers are saved. When an ISR is running in a given
register set, the processor takes an interrupt in the same register set if it has a
higher interrupt level.
This technique can result in a priority inversion.
RIL
RIL
1
2
3
4
5
6
7
1
2
3
4
5
6
7
and
Table 3–37
illustrate the validity of register set assignments when
Register Set 1
Register Set 1
IRQ0
IRQ1
IRQ3
IRQ0
IRQ1
IRQ3
December 2010 Altera Corporation
Chapter 3: Programming Model
Register Set 2
Register Set 2
IRQ2
IRQ4
IRQ5
IRQ6
IRQ2
IRQ4
IRQ5
IRQ6
Exception Processing