IPR-NIOS Altera, IPR-NIOS Datasheet - Page 31

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
Exception and Interrupt Controllers
December 2010 Altera Corporation
External Interrupt Controller Interface
Internal Interrupt Controller
f
1
All exceptions are precise. Precise means that the processor has completed execution
of all instructions preceding the faulting instruction and not started execution of
instructions following the faulting instruction. Precise exceptions allow the processor
to resume program execution once the exception handler clears the exception.
An EIC is typically used in conjunction with shadow register sets to provide
high-performance hardware interrupts. The Nios II processor connects to an EIC
through the EIC interface. When an EIC is present, the internal interrupt controller is
not implemented, and SOPC Builder connects interrupts to the EIC.
The EIC selects among active interrupts and presents one interrupt to the Nios II
processor, with interrupt handler address and register set selection information. The
interrupt selection algorithm is specific to the EIC implementation, and is typically
based on interrupt priorities. The Nios II processor does not depend on any specific
interrupt prioritization scheme in the EIC.
For every external interrupt, the EIC presents an interrupt level. The Nios II processor
uses the interrupt level in determining when to service the interrupt.
Any external interrupt can be configured as an NMI. NMIs are not masked by the
status.PIE bit, and have no interrupt level.
An EIC can be software-configurable.
When the EIC interface and shadow register sets are implemented on the Nios II core,
you must ensure that your software is built with the Nios II EDS version 9.0 or higher.
Earlier versions have an implementation of the eret instruction that is incompatible
with shadow register sets.
For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the
Embedded Peripherals IP User
Processing” in the
Handbook.
The Nios II architecture supports 32 internal hardware interrupts. The processor core
has 32 level-sensitive interrupt request (IRQ) inputs, irq0 through irq31, providing a
unique input for each interrupt source. IRQ priority is determined by software. The
architecture supports nested interrupts.
The software can enable and disable any interrupt source individually through the
ienable control register, which contains an interrupt-enable bit for each of the IRQ
inputs. Software can enable and disable interrupts globally using the PIE bit of the
status control register. A hardware interrupt is generated if and only if all of the
following conditions are true:
■
■
■
The PIE bit of the status register is 1
An interrupt-request input, irq<n>, is asserted
The corresponding bit n of the ienable register is 1
Programming Model
Guide. For details about EIC usage, refer to “Exception
chapter of the Nios II Processor Reference
Nios II Processor Reference Handbook
2–9