IPR-NIOS Altera, IPR-NIOS Datasheet - Page 142

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–10
Nios II Processor Reference Handbook
Tightly-Coupled Memory
Memory Management Unit
Memory Protection Unit
f
The Nios II/f core provides optional tightly-coupled memory interfaces for both
instructions and data. A Nios II/f core can use up to four each of instruction and data
tightly-coupled memories. When a tightly-coupled memory interface is enabled, the
Nios II core includes an additional memory interface master port. Each
tightly-coupled memory interface must connect directly to exactly one memory slave
port.
When tightly-coupled memory is present, the Nios II core decodes addresses
internally to determine if requested instructions or data reside in tightly-coupled
memory. If the address resides in tightly-coupled memory, the Nios II core fetches the
instruction or data through the tightly-coupled memory interface. Software accesses
tightly-coupled memory with the usual load and store instructions, such as ldw or
ldwio.
Accessing tightly-coupled memory bypasses cache memory. The processor core
functions as if cache were not present for the address span of the tightly-coupled
memory. Instructions for managing cache, such as initd and flushd, do not affect the
tightly-coupled memory, even if the instruction specifies an address in
tightly-coupled memory.
When the MMU is present, tightly-coupled memories are always mapped into the
kernel partition and can only be accessed in supervisor mode.
The Nios II/f core provides options to improve the performance of the Nios II MMU.
For details on the MMU architecture, refer to the
Nios II Processor Reference Handbook.
Micro Translation Lookaside Buffers
The translation lookaside buffer (TLB) consists of one main TLB stored in on-chip
RAM and two separate micro TLBs (μTLB) for instructions (μITLB) and data (μDTLB)
stored in LE-based registers.
The μTLBs have a configurable number of entries and are fully associative. The
default configuration has 6 μDTLB entries and 4 μITLB entries. The hardware chooses
the least-recently used μTLB entry when loading a new entry.
The μTLBs are not visible to software. They act as an inclusive cache of the main TLB.
The processor firsts look for a hit in the μTLB. If it misses, it then looks for a hit in the
main TLB. If the main TLB misses, the processor takes an exception. If the main TLB
hits, the TLB entry is copied into the μTLB for future accesses.
The hardware automatically flushes the μTLB on each TLB write operation and on a
wrctl to the tlbmisc register in case the process identifier (PID) has changed.
The Nios II/f core provides options to improve the performance of the Nios II MPU.
For details on the MPU architecture, refer to the
Nios II Processor Reference Handbook.
Programming Model
Programming Model
Chapter 5: Nios II Core Implementation Details
December 2010 Altera Corporation
chapter of the
chapter of the
Nios II/f Core