IPR-NIOS Altera, IPR-NIOS Datasheet - Page 175

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Application Binary Interface
ABI for Linux Systems
Table 7–4. Nios II Relocation Calculation (Part 3 of 3)
ABI for Linux Systems
December 2010 Altera Corporation
R_NIOS2_TLS_TPREL
R_NIOS2_COPY
R_NIOS2_GLOB_DAT
R_NIOS2_JUMP_SLOT
R_NIOS2_RELATIVE
R_NIOS2_GOTOFF
Notes to
(1) For relocation types where no overflow check is performed, the relocated address is truncated to fit the instruction.
(2) Expressions in this column use the following conventions:
(3) Relocation support is provided for Linux systems.
■
■
■
■
■
■
■
■
S: Symbol address
A: Addend
PC: Program counter
GP: Global pointer
Adj(X): (((X >> 16) & 0xFFFF) + ((X >> 15) & 0x1)) & 0xFFFF
BA: The base address at which a shared library is loaded
GOT: The value of the Global Offset Table (GOT) pointer (Linux only)
G: The offset into the GOT for the GOT slot for symbol S (Linux only)
Table
Name
7–4:
(3)
(3)
(3)
(3)
With the information in
manipulating it as an unsigned 32-bit integer, as follows:
Xr = (( R << B ) & M | ( X & ~M ));
where:
■
■
■
■
■
This section describes details specific to Linux systems beyond the Linux-specific
information in
(3)
(3)
R is the relocated address, calculated as shown in
B is the bit shift shown in
M is the bit mask shown in
X is the original instruction
Xr is the relocated instruction
Value
35
36
37
38
39
40
Table 7–2 on page 7–2
check
Overflow
No
No
No
No
No
No
(1)
Table
Refer to
page 7–13
Refer to
page 7–13
S
Refer to
page 7–13
BA+A
S+A
Table 7–4
7–4, any Nios II instruction can be relocated by
Table 7–4
Relocated Address
“Thread-Local Storage” on
“Copy Relocation” on
“Jump Slot Relocation” on
and
R
Table 7–4 on page
(2)
Table 7–4
Nios II Processor Reference Handbook
7–9.
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
Bit Mask
n/a
M
Bit Shift
n/a
B
0
0
0
0
0
7–11