IPR-NIOS Altera, IPR-NIOS Datasheet - Page 43

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
JTAG Debug Module
December 2010 Altera Corporation
Trace Capture
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Trace capture refers to ability to record the instruction-by-instruction execution of the
processor as it executes code in real-time. The JTAG debug module offers the
following trace features:
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Certain trace features require additional licensing or debug tools from third-party
debug providers. For example, an on-chip trace buffer is a standard feature of the
Nios II processor, but using an off-chip trace buffer requires additional debug
software and hardware provided by First Silicon Solutions (FS2) or Lauterbach
GmbH.
For details, refer to the FS2 website (www.fs2.com) and the Lauterbach GmbH
website (www.lauterbach.com).
Execution vs. Data Trace
The JTAG debug module supports tracing the instruction bus (execution trace), the
data bus (data trace), or both simultaneously. Execution trace records only the
addresses of the instructions executed, enabling you to analyze where in memory (i.e.,
in which functions) code executed. Data trace records the data associated with each
load and store operation on the data bus.
The JTAG debug module can filter the data bus trace in real time to capture the
following:
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Capture execution trace (instruction bus cycles).
Capture data trace (data bus cycles).
For each data bus cycle, capture address, data, or both.
Start and stop capturing trace in real time, based on triggers.
Manually start and stop trace under host control.
Optionally stop capturing trace when trace buffer is full, leaving the processor
executing.
Store trace data in on-chip memory buffer in the JTAG debug module. (This
memory is accessible only through the JTAG connection.)
Store trace data to larger buffers in an off-chip debug probe.
Load addresses only
Store addresses only
Both load and store addresses
Load data only
Load address and data
Store address and data
Address and data for both loads and stores
Single sample of the data bus upon trigger event
Nios II Processor Reference Handbook
2–21