IPR-NIOS Altera, IPR-NIOS Datasheet - Page 54

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–8
Memory Protection Unit
Nios II Processor Reference Handbook
Memory Regions
f
The TLB lookup algorithm for data accesses is shown in
Example 3–2. TLB Lookup Algorithm for Data Access Operations
if (VPN match && (G == 1 || PID match))
else
Refer to
The Nios II processor provides an MPU for operating systems and runtime
environments that desire memory protection but do not require virtual memory
management. For information about memory protection with virtual memory
management, refer to
When present and enabled, the MPU monitors all Nios II instruction fetches and data
memory accesses to protect against errant software execution. The MPU is a hardware
facility that system software uses to define memory regions and their associated
access permissions. The MPU triggers an exception if software attempts to access a
memory region in violation of its permissions, allowing you to intervene and handle
the exception as appropriate. The precise exception effectively prevents the illegal
access to memory.
The MPU extends the Nios II processor to support user mode and supervisor mode.
Typically, system software runs in supervisor mode and end-user applications run in
user mode, although all software can run in supervisor mode if desired. System
software defines which MPU regions belong to supervisor mode and which belong to
user mode.
The MPU contains up to 32 instruction regions and 32 data regions. Each region is
defined by the following attributes:
■
■
■
■
■
■
Base address
Region type
Region index
Region size or upper address limit
Access permissions
Default cacheability (data regions only)
if ((load && R == 1) || (store && W == 1) || flushda)
else
if (EH bit of status register == 1)
else
PADDR = concatenate(PFN, VADDR[11:0])
take TLB permission violation exception
take double TLB miss exception
take fast TLB miss exception
“Instruction-Related Exceptions” on page 3–39
“Memory Management Unit” on page
for details on TLB exceptions.
Example
December 2010 Altera Corporation
3–3.
Chapter 3: Programming Model
3–2.
Memory Protection Unit