IPR-NIOS Altera, IPR-NIOS Datasheet - Page 166

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–2
Memory Alignment
Register Usage
Nios II Processor Reference Handbook
Contents in memory are aligned as follows:
■
■
■
■
The ABI adds additional usage conventions to the Nios II register file defined in the
Programming Model
the registers as shown in
Table 7–2. Nios II ABI Register Usage (Part 1 of 2)
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
Register
A function must be aligned to a minimum of 32-bit boundary.
The minimum alignment of a data element is its natural size. A data element larger
than 32 bits need only be aligned to a 32-bit boundary.
Structures, unions, and strings must be aligned to a minimum of 32 bits.
Bit fields inside structures are always 32-bit aligned.
zero
at
et
Name
chapter of the Nios II Processor Reference Handbook. The ABI uses
Compiler
Used by
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table
7–2.
Saved
Callee
v
v
v
v
v
v
(2)
(3)
(1)
0x00000000
Assembler temporary
Return value (least-significant 32 bits)
Return value (most-significant 32 bits)
Register arguments (first 32 bits)
Register arguments (second 32 bits)
Register arguments (third 32 bits)
Register arguments (fourth 32 bits)
Caller-saved general-purpose registers
Callee-saved general-purpose registers
Exception temporary
Chapter 7: Application Binary Interface
Normal Usage
December 2010 Altera Corporation
Memory Alignment