IPR-NIOS Altera, IPR-NIOS Datasheet - Page 233

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
custom
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
B
if c == 1
then rC ← f
else Ø ← f
custom N, xC, xA, xB
Where xA means either general purpose register rA, or custom register cA.
custom 0, c6, r7, r8
The custom opcode provides access to up to 256 custom instructions allowed by the Nios II
architecture. The function implemented by a custom instruction is user-defined and is specified
at system generation time. The 8-bit immediate N field specifies which custom instruction to
use. Custom instructions can use up to two parameters, xA and xB, and can optionally write the
result to a register xC.
To access a custom register inside the custom instruction logic, clear the bit readra, readrb, or
writerc that corresponds to the register field. In assembler syntax, the notation cN refers to
register N in the custom register file and causes the assembler to clear the c bit of the opcode.
For example, custom 0, c3, r5, r0 performs custom instruction 0, operating on
general-purpose registers r5 and r0, and stores the result in custom register 3.
None
R
A = Register index of operand A
B = Register index of operand B
C = Register index of operand C
readra = 1 if instruction uses rA, 0 otherwise
readrb = 1 if instruction uses rB, 0 otherwise
writerc = 1 if instruction provides result for rC, 0 otherwise
N = 8-bit number that selects instruction
23
22
21
N
(rA, rB, A, B, C)
N
(rA, rB, A, B, C)
20
19
C
18
17
16
15
14
13
12
11
10
N
9
8
Nios II Processor Reference Handbook
7
custom instruction
6
5
4
0x32
3
2
1
8–47
0