IPR-NIOS Altera, IPR-NIOS Datasheet - Page 119

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Advanced Features Page
December 2010 Altera Corporation
External Interrupt Controller Interface
f
f
1
■
For further descriptions of exceptions, exception handling, and control registers, refer
to the
The Interrupt controller setting determines which of the following configurations is
implemented:
■
■
The EIC interface is available only on the Nios II/f core.
When the EIC interface and shadow register sets are implemented on the Nios II core,
you must ensure that your software is built with the Nios II Embedded Design Suite
(EDS) version 9.0 or higher. Earlier versions have an implementation of the eret
instruction that is incompatible with shadow register sets.
For details about the EIC controller, refer to “Exception Processing” in the
Programming Model
1
There are two misaligned memory address exceptions:
■
■
Extra exception information—When Extra exception information is on, nonbreak
exceptions store a code in the CAUSE field of the exception control register to
indicate the cause of the exception.
1
Your exception handler can use this code to quickly determine the proper action to
take, rather than have to determine the cause of an exception through instruction
decoding. Additionally, some exceptions also store the instruction or data address
associated with the exception in the badaddr register.
Internal interrupt controller
External interrupt controller (EIC) interface
Programming Model
Misaligned data address—Data addresses of load and store instructions are
checked for misalignment. A data address is considered misaligned if the byte
address is not a multiple of the data width of the load or store instruction (4
bytes for word, 2 bytes for half-word). Byte load and store instructions are
always aligned so never generate a misaligned data address exception.
Misaligned destination address—Destination instruction addresses of br,
callr, jmp, ret, eret, and bret instructions are checked for misalignment. A
destination instruction address is considered misaligned if the target byte
address of the instruction is not a multiple of four.
When your system contains an MMU or MPU, the processor automatically
generates misaligned memory access exceptions. Therefore, the Misaligned
memory access checkbox is always disabled when Include MMU or
Include MPU on the Core Nios II page are on.
When your system contains an MMU or MPU, the processor automatically
generates extra exception information. Therefore, the Extra exception
information setting is always disabled when the Core Nios II page Include
MMU or Include MPU are on.
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook.
Nios II Processor Reference Handbook
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