IPR-NIOS Altera, IPR-NIOS Datasheet - Page 24

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–2
Figure 2–1. Nios II Processor Core Block Diagram
Processor Implementation
Nios II Processor Reference Handbook
to software
debugger
interface
JTAG
Signals
Custom
I/O
eic_port_data[44..0]
eic_port_valid
reset
clock
cpu_resetrequest
The following sections discuss hardware implementation details related to each
functional unit.
The functional units of the Nios II architecture form the foundation for the Nios II
instruction set. However, this does not indicate that any unit is implemented in
hardware. The Nios II architecture describes an instruction set, not a particular
hardware implementation. A functional unit can be implemented in hardware,
emulated in software, or omitted entirely.
A Nios II implementation is a set of design choices embodied by a particular Nios II
processor core. All implementations support the instruction set defined in the
Instruction Set Reference
implementation achieves specific objectives, such as smaller core size or higher
performance. This allows the Nios II architecture to adapt to the needs of different
target applications.
Implementation variables generally fit one of three trade-off patterns: more or less of a
feature; inclusion or exclusion of a feature; hardware implementation or software
emulation of a feature. An example of each trade-off follows:
cpu_resettaken
irq[31..0]
Debug Module
Instruction
Custom
JTAG
Logic
Nios II Processor Core
Key
Generation
Controller
Controller
Exception
Controller
Controller
Interface
Interrupt
External
Interrupt
Program
Internal
Address
&
chapter of the Nios II Processor Reference Handbook. Each
Arithmetic
Logic Unit
Required
Module
Protection
Registers
Instruction
Registers
Purpose
Register
Regions
General
Shadow
Regions
Memory
Control
Sets
Data
Unit
Optional
Module
Management
Instruction
Translation
Lookaside
Memory
Cache
Buffer
Cache
Unit
Data
December 2010 Altera Corporation
Chapter 2: Processor Architecture
Instruction Bus
Data Bus
Instruction Memory
Instruction Memory
Processor Implementation
Tightly Coupled
Tightly Coupled
Tightly Coupled
Tightly Coupled
Data Memory
Data Memory