IPR-NIOS Altera, IPR-NIOS Datasheet - Page 149

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/s Core
Table 5–13. Instruction Byte Address Fields
December 2010 Altera Corporation
31
30
29
Tightly-Coupled Memory
Execution Pipeline
28
27
26
tag
Instruction Cache
The instruction cache for the Nios II/s core is nearly identical to the instruction cache
in the Nios II/f core. The instruction cache memory has the following characteristics:
■
■
■
Table 5–13
The size of the tag field depends on the size of the cache memory and the physical
address size. The size of the line field depends only on the size of the cache memory.
The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte
address size is 31 bits.
The instruction cache is optional. However, excluding instruction cache from the
Nios II/s core requires that the core include at least one tightly-coupled instruction
memory.
The Nios II/s core provides optional tightly-coupled memory interfaces for
instructions. A Nios II/s core can use up to four tightly-coupled instruction
memories. When a tightly-coupled memory interface is enabled, the Nios II core
includes an additional memory interface master port. Each tightly-coupled memory
interface must connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes addresses
internally to determine if requested instructions reside in tightly-coupled memory. If
the address resides in tightly-coupled memory, the Nios II core fetches the instruction
through the tightly-coupled memory interface. Software does not require awareness
of whether code resides in tightly-coupled memory or not.
Accessing tightly-coupled memory bypasses cache memory. The processor core
functions as if cache were not present for the address span of the tightly-coupled
memory. Instructions for managing cache, such as initi and flushi, do not affect the
tightly-coupled memory, even if the instruction specifies an address in
tightly-coupled memory.
This section provides an overview of the pipeline behavior for the benefit of
performance-critical applications. Designers can use this information to minimize
unnecessary processor stalling. Most application programmers never need to analyze
the performance of individual instructions.
25
Direct-mapped cache implementation
The instruction master port reads an entire cache line at a time from memory, and
issues one read per clock cycle.
Critical word first
24
23
22
shows the instruction byte address fields.
21
20
19
18
17
16
15
14
13
12
line
11
10
9
8
Nios II Processor Reference Handbook
7
6
5
4
3
offset
2
1
5–17
0