IPR-NIOS Altera, IPR-NIOS Datasheet - Page 44

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–22
Referenced Documents
Document Revision History
Table 2–8. Document Revision History (Part 1 of 2)
Nios II Processor Reference Handbook
December 2010
July 2010
November 2009
March 2009
Date
10.1.0
10.0.0
Version
9.1.0
9.0.0
Trace Frames
A frame is a unit of memory allocated for collecting trace data. However, a frame is
not an absolute measure of the trace depth.
To keep pace with the processor executing in real time, execution trace is optimized to
store only selected addresses, such as branches, calls, traps, and interrupts. From
these addresses, host-side debug software can later reconstruct an exact
instruction-by-instruction execution trace. Furthermore, execution trace data is stored
in a compressed format, such that one frame represents more than one instruction. As
a result of these optimizations, the actual start and stop points for trace collection
during execution might vary slightly from the user-specified start and stop points.
Data trace stores 100% of requested loads and stores to the trace buffer in real time.
When storing to the trace buffer, data trace frames have lower priority than execution
trace frames. Therefore, while data frames are always stored in chronological order,
execution and data trace are not guaranteed to be exactly synchronized with each
other.
This chapter references the following documents:
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Table 2–8
Programming Model
Instantiating the Nios II Processor in SOPC Builder
Reference Handbook
Nios II Core Implementation Details
Handbook
Instruction Set Reference
Vectored Interrupt Controller chapter in the
Nios II Custom Instruction User Guide
Avalon Interface Specifications
Using Tightly Coupled Memory with the Nios II Processor
AN 391: Profiling Nios II Systems
Literature: Megafunctions
Added reference to tightly-coupled memory tutorial.
Maintenance release.
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Maintenance release.
Added external interrupt controller interface information.
Added shadow register set information.
shows the revision history for this document.
chapter of the Nios II Processor Reference Handbook
chapter of the Nios II Processor Reference Handbook
page on the Altera website
chapter of the Nios II Processor Reference
Changes
Embedded Peripherals IP User Guide
chapter of the Nios II Processor
December 2010 Altera Corporation
Chapter 2: Processor Architecture
Referenced Documents