IPR-NIOS Altera, IPR-NIOS Datasheet - Page 68

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–22
Table 3–22. config Control Register Field Descriptions
Table 3–23. mpubase Control Register Fields
.
Table 3–24. mpubase Control Register Field Descriptions
Nios II Processor Reference Handbook
PE
ANI
31
Notes to
(1) This field size is variable. Unused upper bits must be written as zero.
(2) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
BASE
INDEX
D
0
Field
30
Field
29
Table
28
3–23:
PE is the memory protection enable bit. When PE =1, the MPU is
enabled. When PE = 0, the MPU is disabled. In systems without an
MPU, PE is always zero.
ANI is the automatic nested interrupt mode bit. If ANI is set to zero,
the processor clears status.PIE on each interrupt, disabling fast
nested interrupts. If ANI is set to one, the processor leaves
status.PIE set to one at the time of an interrupt, enabling fast
nested interrupts.
If the EIC interface and shadow register sets are not implemented in
the Nios II core, ANI always reads as zero, disabling fast nested
interrupts.
BASE is the base memory address of the region identified by the
INDEX and D fields.
INDEX is the region index number.
D is the region access bit. When D =1, INDEX refers to a data region.
When D = 0, INDEX refers to an instruction region.
27
26
Table 3–22
The mpubase Register
The mpubase register works in conjunction with the mpuacc register to set and retrieve
MPU region information and is only available in systems with an MPU.
shows the layout of the mpubase register.
Table 3–24
The BASE field specifies the base address of an MPU region. The 25-bit BASE field
corresponds to bits 6 through 30 of the base address, making the base address always
a multiple of 64 bytes. If the minimum region size set in SOPC Builder at generation
time is larger than 64 bytes, unused low-order bits of the BASE field must be written as
zero and are read as zero. For example, if the minimum region size is 1024 bytes, the
four least-significant bits of the BASE field (bits 6 though 9 of the mpubase register)
must be zero. Similarly, if the Nios II address space is less than 31 bits, unused
high-order bits must also be written as zero and are read as zero.
25
24
23
22
gives details of the fields defined in the config register
gives details of the fields defined in the mpubase register
21
Description
20
Description
19
BASE
18
(2)
17
16
15
14
13
12
11
10
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
9
Access
Access
8
December 2010 Altera Corporation
7
Chapter 3: Programming Model
6
Reset
Reset
5
0
0
0
0
0
INDEX
4
Table 3–23
Only with the
EIC interface
and shadow
register sets
3
Available
Available
Only with
Only with
Only with
Only with
(1)
MPU
MPU
MPU
MPU
2
Registers
1
D
0