IPR-NIOS Altera, IPR-NIOS Datasheet - Page 41

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
JTAG Debug Module
December 2010 Altera Corporation
JTAG Target Connection
Download and Execute Software
Software Breakpoints
Hardware Breakpoints
Hardware Triggers
1
The following sections describe the capabilities of the Nios II JTAG debug module
hardware. The usage of all hardware features is dependent on host software, such as
the Nios II Software Build Tools for Eclipse, which manages the connection to the
target processor and controls the debug process.
The JTAG target connection provides the ability to connect to the processor through
the standard JTAG pins on the Altera FPGA. This provides basic capabilities to start
and stop the processor, and examine and edit registers and memory. The JTAG target
connection is the minimum requirement for the Nios II flash programmer.
While the processor has no minimum clock frequency requirements, Altera
recommends that your design’s system clock frequency be at least four times the
JTAG clock frequency to ensure that the on-chip instrumentation (OCI) core functions
properly.
Downloading software refers to the ability to download executable code and data to
the processor’s memory via the JTAG connection. After downloading software to
memory, the JTAG debug module can then exit debug mode and transfer execution to
the start of executable code.
Software breakpoints allow you to set a breakpoint on instructions residing in RAM.
The software breakpoint mechanism writes a break instruction into executable code
stored in RAM. When the processor executes the break instruction, control is
transferred to the JTAG debug module.
Hardware breakpoints allow you to set a breakpoint on instructions residing in
nonvolatile memory, such as flash memory. The hardware breakpoint mechanism
continuously monitors the processor’s current instruction address. If the instruction
address matches the hardware breakpoint address, the JTAG debug module takes
control of the processor.
Hardware breakpoints are implemented using the JTAG debug module’s hardware
trigger feature.
Hardware triggers activate a debug action based on conditions on the instruction or
data bus during real-time program execution. Triggers can do more than halt
processor execution. For example, a trigger can be used to enable trace data collection
during real-time processor execution.
Nios II Processor Reference Handbook
2–19