IPR-NIOS Altera, IPR-NIOS Datasheet - Page 76

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–30
Exception Processing
Nios II Processor Reference Handbook
MPU Initialization
Debugger Access
Terminology
1
Normally, a wrctl instruction flushes the pipeline to guarantee that any side effects of
writing control registers take effect immediately after the wrctl instruction completes
execution. However, wrctl instructions to the mpubase and mpuacc control registers do
not automatically flush the pipeline. Instead, system software is responsible for
flushing the pipeline as needed (either by using a flushp instruction or a wrctl
instruction to a register that does flush the pipeline). Because a context switch
typically requires reprogramming the MPU regions for the new thread, flushing the
pipeline on each wrctl instruction would create unnecessary overhead.
Your system software must provide a data structure that contains the region
information described in
data structure ideally contains two 32-bit values that correspond to the mpubase and
mpuacc register formats.
The MPU is disabled on system reset. Before enabling the MPU, Altera recommends
initializing all MPU regions. Enable desired instruction and data regions by writing
each region’s attributes to the mpubase and mpuacc registers as described in
Region Read and Write Operations” on page
regions. When using region size, clear mpuacc.MASK to zero. When using limit, set the
mpubase.BASE to a nonzero value and clear mpuacc.LIMIT to zero.
You must enable at least one instruction and one data region, otherwise unpredictable
behavior might occur.
To perform a context switch, use a wrctl to write a zero to the PE field of the config
register to disable the MPU, define all MPU regions from the new thread’s data
structure, and then use another wrctl to write a one to config.PE to enable the MPU.
Define each region using the pair of wrctl instructions described in
Read and Write Operations” on page
sequence until all desired regions are defined.
The debugger can access all MPU-related control registers using the normal wrctl and
rdctl instructions. During debugging, the Nios II ignores the MPU, effectively
temporarily disabling it.
Exception processing is the act of responding to an exception, and then returning, if
possible, to the pre-exception execution state.
All Nios II exceptions are precise. Precise exceptions enable the system software to
re-execute the instruction, if desired, after handling the exception.
Altera Nios II documentation uses the following terminology to discuss exception
processing:
“Memory Regions” on page 3–8
3–29. Repeat this dual wrctl instruction
3–29. You must also disable unused
for each active thread. The
December 2010 Altera Corporation
Chapter 3: Programming Model
“MPU Region
Exception Processing
“MPU